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5-Bit Programmable 2-/3-/4-Phase Synchronous Buck Controller ADP3186
FEATURES
Selectable 2-, 3-, or 4-phase operation at up to 1 MHz per phase 1% worst-case differential sensing error over temperature Logic-level PWM outputs for interface to external high power drivers Active current balancing between all output phases Built-in power good/crowbar blanking supports on-the-fly VID code changes 5-bit digitally programmable 0.8 V to 1.55 V output Programmable short-circuit protection with programmable latch-off delay
FUNCTIONAL BLOCK DIAGRAM
VCC
28
RAMPADJ
14
RT
13
ADP3186
UVLO SHUTDOWN AND BIAS
EN 11
OSCILLATOR SET EN
27 PWM1
GND 19
CMP
RESET
CROWBAR 6 CSREF 2.1V
CMP CURRENT BALANCING CIRCUIT CMP
RESET 2-/3-/4-PHASE DRIVER LOGIC RESET
26 PWM2
25 PWM3
DAC + 300mV CSREF
CMP
RESET
24 PWM4
CROWBAR
CURRENT LIMIT
APPLICATIONS
Desktop PC power supplies for AMD OpteronTM processors VRM modules
DAC - 300mV
23 SW1
PWRGD 10
DELAY
22 SW2 21 SW3
ILIMIT 15 EN
20 SW4
GENERAL DESCRIPTION
The ADP3186 is a highly efficient multiphase synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance AMD processors. It uses an internal 5-bit DAC to read a voltage identification (VID) code directly from the processor, which is used to set the output voltage between 0.8 V and 1.55 V. It uses a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing the construction of up to four complementary buck switching stages. The ADP3186 includes programmable no-load offset and slope functions to adjust the output voltage as a function of the load current, so that it is always optimally positioned for a system transient. The ADP3186 also provides accurate and reliable short-circuit protection, adjustable current limiting, and a power good output that accommodates on-the-fly output voltage changes requested by the CPU. The ADP3186 is specified over the commercial temperature range of 0C to 85C and is available in 28-lead TSSOP and QSOP packages.
DELAY 12 SOFT START
CURRENT LIMIT CIRCUIT
17 CSSUM
16 CSREF
18 CSCOMP
8
COMP 9
FB
PRECISION REFERENCE
VID DAC
04914-0-001
7
1
2
3
4
5
FBRTN
VID4
VID3
VID2
VID1
VID0
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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ADP3186 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Specifications..................................................................................... 3 Test Circuits....................................................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ........................................................................ 9 Start-Up Sequence........................................................................ 9 Master Clock Frequency.............................................................. 9 Output Voltage Differential Sensing .......................................... 9 Output Current Sensing .............................................................. 9 Active Impedance Control Mode............................................. 10 Current Control Mode and Thermal Balance ........................ 10 Voltage Control Mode................................................................ 10 Soft Start ...................................................................................... 10 Current Limit, Short-Circuit, and Latch-Off Protection ...... 11 Dynamic VID.............................................................................. 11 Power Good Monitoring ........................................................... 12 Output Crowbar ......................................................................... 12 Output Enable and UVLO ........................................................ 12 Application Information................................................................ 14 Setting the Clock Frequency..................................................... 14 Soft Start and Current Limit Latch-Off Delay Times............ 14 Inductor Selection ...................................................................... 14 Designing an Inductor............................................................... 15 Selecting a Standard Inductor .............................................. 15 Output Droop Resistance.......................................................... 15 Inductor DCR Temperature Correction ................................. 16 Output Offset .............................................................................. 16 COUT Selection ............................................................................. 17 Power MOSFETs......................................................................... 17 Ramp Resistor Selection............................................................ 18 COMP Pin Ramp ....................................................................... 19 Current Limit Setpoint .............................................................. 19 Feedback Loop Compensation Design.................................... 19 CIN Selection and Input Current di/dt Reduction.................. 20 Tuning Procedure....................................................................... 21 DC Loadline Setting .............................................................. 21 AC Loadline Setting............................................................... 21 Initial Transient Setting ......................................................... 22 Layout and Component Placement ......................................... 22 General Recommendations .................................................. 22 Power Circuitry Recommendations .................................... 23 Signal Circuitry Recommendations .................................... 23 Outline Dimensions ....................................................................... 24 Ordering Guide .......................................................................... 24
REVISION HISTORY
3/06--Rev. 0 to Rev. A Updated ADP3110 to ADP3110A................................. Universal Changes to Table 1.......................................................................... 3 Added QSOP Package.................................................................. 24 Updated Ordering Guide............................................................. 24 8/04--Revision Sp0: Initial Version
Rev. A | Page 2 of 24
ADP3186 SPECIFICATIONS
VCC = 12 V, FBRTN = GND, TA = 0C to 85C, unless otherwise specified. 1 Table 1.
Parameter ERROR AMPLIFIER Output Voltage Range 2 Accuracy 0.8 V Output Symbol VCOMP VFB Referenced to FBRTN, CSSUM = CSCOMP, Figure 2 TSSOP QSOP Referenced to FBRTN, CSSUM = CSCOMP, Figure 2 TSSOP QSOP Referenced to FBRTN, CSSUM = CSCOMP, Figure 2 TSSOP QSOP VCC = 10 V to 14 V Conditions Min 0.5 Typ Max 3.5 Unit V
0.7920 0.7880
0.8080 0.8120
V V
1.175 V Output
1.1633 1.1574
1.1868 1.1926
V V
1.55 V Output
1.5345 1.5268 -13 0.05 -15.5 100 500 20 25
1.5655 1.5733 -17 200
Line Regulation Input Bias Current FBRTN Current Output Current Gain Bandwidth Product Slew Rate VID INPUTS Input Low Voltage Input High Voltage Input Current, Input Voltage Low Pull-Up Resistance Internal Pull-Up Voltage VID Transition Delay Time2 No CPU Detection Turn-Off Delay Time2 OSCILLATOR Frequency Range2 Frequency Variation
VFB IFB IFBRTN IO(ERR) GBW(ERR)
V V % A A A MHz V/s V V A k V ns ns
FB Forced to VOUT - 3% COMP = FB CCOMP = 10 pF
VIL(VID) VIH(VID) IIL(VID) RVID
0.8 1.5 VID(X) = 0 V 100 2.0 400 400 20 120 2.4 26 2.65
VID code change to FB change VID code change to 11111 to PWM going low fOSC fPHASE
Output Voltage Timing Resistor Value RAMPADJ Output Voltage RAMPADJ Input Current Range CURRENT SENSE AMPLIFIER Offset Voltage
VRT VRAMPADJ IRAMPADJ VOS(CSA)
TA = 25C, RT = 250 k, 4-phase TA = 25C, RT = 115 k, 4-phase TA = 25C, RT = 75 k, 4-phase RT = 100 k to GND RAMPADJ - FB
0.25 155
1.9 -50 0
200 400 600 2.0
4 245
2.1 500 +50 50
MHz kHz kHz kHz V k mV A
CSSUM - CSREF, Figure 3 TSSOP QSOP
Input Bias Current Gain Bandwidth Product Slew Rate Input Common-Mode Range
IBIAS(CSSUM) GBW(CSA) CCSCOMP = 10 pF CSSUM and CSREF
Rev. A | Page 3 of 24
-3 -3.5 -50 10 10 0
+3 +3.5 +50
2.7
mV mV nA MHz V/s V
ADP3186
Parameter Positioning Accuracy Output Voltage Range Output Current CURRENT BALANCE CIRCUIT Common-Mode Range Input Resistance Input Current Input Current Matching CURRENT LIMIT COMPARATOR Output Voltage Normal Mode Shutdown Mode Output Current, Normal Mode Maximum Output Current2 Current Limit Threshold Voltage Current Limit Setting Ratio DELAY Normal Mode Voltage DELAY Overcurrent Threshold Latch-Off Delay Time SOFT START Output Current, Soft Start Mode Soft Start Delay Time ENABLE INPUT Input Low Voltage Input High Voltage Input Current, Input Voltage Low POWER GOOD COMPARATOR Undervoltage Threshold Overvoltage Threshold Output Low Voltage OFF_State Leakage Current Power Good Delay Time VID Code Changing VID Code Static Crowbar Trip Point Crowbar Reset Point Crowbar Delay Time VID Code Changing VID Code Static PWM OUTPUTS Output Low Voltage Output High Voltage SUPPLY DC Supply Current UVLO Threshold Voltage UVLO Hysteresis
1 2
Symbol VFB ICSCOMP VSW(X)CM RSW(X) ISW(X) ISW(X)
Conditions Figure 4
Min -77 0.05
Typ -80 500
Max -83 2.7
Unit mV V A mV k A %
SW(X) = 0 V SW(X) = 0 V SW(X) = 0 V
-600 20 4 -5
30 7
+200 40 10 +5
VILIMIT(NM) VILIMIT(SD) IILIMIT(NM) VCL VDELAY(NM) VDELAY(OC) tDELAY IDELAY(SS) tDELAY(SS)
EN > 2.0 V, RILIMIT = 250 k EN < 0.8 V, IILIMIT = -100 A EN > 2.0 V, RILIMIT = 250 k VCSREF - VCSCOMP, RILIMIT = 250 k VCL/IILIMIT RDELAY = 250 k RDELAY = 250 k RDELAY = 250 k, CDELAY = 12 nF During startup, DELAY < 2.8 V RDELAY = 250 k, CDELAY = 12 nF, VID code = 011111
2.9
3 12
3.1 400
V mV A A mV mV/A V V ms A ms
60 105 2.9 1.7
125 10.4 3 1.8 1.5 20 1
145 3.1 1.9
15
25
VIL(EN) VIH(EN) IIL(EN) VPWRGD(UV) VPWRGD(OV) VOL(PWRGD)
0.8 EN = 0 V Relative to nominal DAC output Relative to nominal DAC output IPWRGD(SINK) = 4 mA VCSREF = VDAC 2.0 -1 -200 200 -300 300 150 +1 -400 400 400 50
V V A mV mV mV A s ns V mV s ns
100 VCROWBAR tCROWBAR Overvoltage to PWM going low 100 2.0 300
250 200 2.1 400 250 400 160 5 5 6.9 0.9
2.2 500
VOL(PWM) VOH(PWM)
IPWM(SINK) = -400 A IPWM(SOURCE) = +400 A
500
4.0
mV V mA V V
VUVLO
VCC rising
6.5 0.7
10 7.3 1.1
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Guaranteed by design or bench characterization, not production tested.
Rev. A | Page 4 of 24
ADP3186 TEST CIRCUITS
ADP3186
1 2 3
VID4 VID3 VID2 VID1 VID0 CROWBAR FBRTN FB COMP PWRGD EN DELAY RT RAMPADJ
VCC 28 PWM1 27 PWM2 26 PWM3 25 PWM4 24 SW1 23 SW2 22 SW3 21 SW4 20 GND 19 CSCOMP 18
+
12V
1F 100n F
5-BIT CODE
4 5 6 7 8 9 1k 10
ADP3186
VCC 12V
28
FB
8
10k
9
COMP 200k
18
CSCOMP
1.25V
11 12
200k
CSSUM
17
20k CSSUM 17 4.7nF 250k
13 14
100nF
80mV
CSREF 16 ILIMIT 15
04914-0-002
CSREF
16
250k
GND
19
Figure 2. Closed-Loop Output Voltage Accuracy
Figure 4. Positioning Voltage
ADP3186
VCC 12V
28
CSCOMP
18
39k
100nF CSSUM
17
1k
16
CSREF
GND
19
VOS =
Figure 3. Current Sense Amplifier, VOS
04914-0-003
1.0V
CSCOMP - 1V 40
Rev. A | Page 5 of 24
04914-0-004
1.0V
ADP3186 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter VCC FBRTN VID0 - VID4, EN, DELAY, ILIMIT, CSCOMP, RT, PWM1-PWM4, COMP, CROWBAR SW1-SW4 All Other Inputs and Outputs Storage Temperature Operating Ambient Temperature Range Operating Junction Temperature Thermal Impedance (JA) Lead Temperature Soldering (10 sec) Infrared (15 sec) Rating -0.3 V to +15 V -0.3 V to +0.3 V -0.3 V to +5.5 V -5 V to +25 V -0.3 V to VCC + 0.3 V -65C to +150C 0C to 85C 125C 100C/W 300C 260C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified all other voltages re referenced to GND.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 6 of 24
ADP3186 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VID4 1 VID3 2 VID2 3 VID1 4 VID0 5 CROWBAR 6 FBRTN 7 FB 8 COMP 9 PWRGD 10 EN 11 DELAY 12 RT 13 RAMPADJ 14
28 27 26 25
VCC PWM1 PWM2 PWM3 PWM4 SW1 SW2 SW3 SW4 GND CSCOMP CSSUM CSREF ILIMIT
04914-0-005
ADP3186
TOP VIEW (Not to Scale)
24 23 22 21 20 19 18 17 16 15
Figure 5. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 to 5 Mnemonic VID4 to VID0 Description Voltage Identification DAC Inputs. These five pins are pulled up to an internal reference, providing a Logic 1, if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.8 V to 1.55 V (see Table 4). Leaving all the VID pins open results in the ADP3186 going into No CPU mode, shutting off its PWM outputs and pulling the PWRGD output low. Crowbar Output. This logic-level output can be used to control an external device to short the 12 V supply to ground to protect the CPU from overvoltage, if CSREF exceeds 2.1 V. Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage. Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between this pin and the output voltage sets the no-load offset point. Error Amplifier Output and Compensation Point. Power Good Output. Open-drain output that signals when the output voltage is outside the proper operating range. Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low. Soft Start Delay and Current Limit Latch-Off Delay Setting Input. An external resistor and capacitor connected between this pin and GND sets the soft start ramp-up time and the overcurrent latch-off delay time. Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device. PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM ramp. Current Limit Setpoint/Enable Output. An external resistor from this pin to GND sets the current limit threshold of the converter. This pin is actively pulled low when the ADP3186 EN input is low, or when VCC is below its UVLO threshold, to signal to the driver IC that the driver high-side and low-side outputs should go low. Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense amplifier and the power good and crowbar functions. This pin should be connected to the common point of the output inductors. Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor currents together to measure the total output current. Current Sense Compensation Point. A resistor and a capacitor from this pin to CSSUM determine the slope of the load line and the positioning loop response time. Ground. All internal biasing and the logic output signals of the device are referenced to this ground. Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should be left open. Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the ADP3110A. Connecting the PWM3 and/or PWM4 outputs to GND causes that phase to turn off, allowing the ADP3186 to operate as a 2-, 3-, or 4-phase controller. Supply Voltage for the Device.
6 7 8 9 10 11 12 13 14 15
CROWBAR FBRTN FB COMP PWRGD EN DELAY RT RAMPADJ ILIMIT
16
CSREF
17 18 19 20 to 23 24 to 27
CSSUM CSCOMP GND SW4 to SW1 PWM4 to PMW1 VCC
28
Rev. A | Page 7 of 24
ADP3186 TYPICAL PERFORMANCE CHARACTERISTICS
4
5.3 TA = 25C 4-PHASE OPERATION
MASTER CLOCK FREQUENCY (MHz)
5.2
SUPPLY CURRENT (mA)
04914-0-006
3
5.1
5.0
2
4.9
1
4.8
4.7
04914-0-007
0 0 50 100 150 200 RT VALUE (k) 250 300
4.6 0 0.5 1 1.5 2 2.5 3 OSCILLATOR FREQUENCY (MHz) 3.5 4
Figure 6. Master Clock Frequency vs. RT
Figure 7. Supply Current vs. Oscillator Frequency
Rev. A | Page 8 of 24
ADP3186 THEORY OF OPERATION
The ADP3186 combines a multimode, fixed frequency PWM control with multiphase logic outputs for use in 2-, 3-, and 4-phase synchronous buck CPU core supply power converters. The internal VID DAC is designed to interface with AMD Opteron CPUs. Multiphase operation is important for producing the high currents and low voltages demanded by today's microprocessors. Handling the high currents in a singlephase converter places high thermal demands on the components in the system such as the inductors and MOSFETs. The multimode control of the ADP3186 ensures a stable, high performance topology for * * * * * * * * * Balancing currents and thermals between phases High speed response at the lowest possible switching frequency and output decoupling Minimizing thermal switching losses due to lower frequency operation Tight loadline regulation and accuracy High current output for up to 4-phase operation Reduced output ripple due to multiphase cancellation PC board layout noise immunity Ease of use and design due to independent component selection Flexibility in operation for tailoring design to low cost or high performance The PWM outputs are logic-level devices intended for driving external gate drivers such as the ADP3110A. Because each phase is monitored independently, operation approaching 100% duty cycle is possible. Also, more than one output can be on at the same time for overlapping phases.
MASTER CLOCK FREQUENCY
The clock frequency of the ADP3186 is set with an external resistor connected from the RT pin to ground. The frequency follows the graph in Figure 6. To determine the frequency per phase, the clock is divided by the number of phases in use. If PWM4 is grounded, then divide the master clock by 3 for the frequency of the remaining phases. If PWM3 and PWM4 are grounded, then divide by 2. If all phases are in use, divide by 4.
OUTPUT VOLTAGE DIFFERENTIAL SENSING
The ADP3186 combines differential sensing with a high accuracy VID DAC and reference and a low offset error amplifier. This maintains a worst-case specification of 1% differential sensing error over its full operating output voltage and temperature range. The output voltage is sensed between the FB and FBRTN pins. FB should be connected through a resistor to the regulation point, usually the remote sense pin of the microprocessor. FBRTN should be connected directly to the remote sense ground point. The internal VID DAC and precision reference are referenced to FBRTN, which has a minimal current of 100 A to allow accurate remote sensing. The internal error amplifier compares the output of the DAC to the FB pin to regulate the output voltage.
START-UP SEQUENCE
During startup, the number of operational phases and their phase relationship is determined by the internal circuitry that monitors the PWM outputs. Normally, the ADP3186 operates as a 4-phase PWM controller. Grounding the PWM4 pin programs 3-phase operation and grounding the PWM3 and PWM4 pins programs 2-phase operation. When the ADP3186 is enabled, the controller outputs a voltage on PWM3 and PWM4 that is approximately 675 mV. An internal comparator checks each pin's voltage versus a threshold of 300 mV. If the pin is grounded, it is below the threshold and the phase is disabled. The output resistance of the PWM pin is approximately 5 k during this detection time. Any external pull-down resistance connected to the PWM pin should not be less than 25 k to ensure proper operation. PWM1 and PWM2 are disabled during the phase detection interval, which occurs during the first two clock cycles of the internal oscillator. After this time, if the PWM output is not grounded, the 5 k resistance is removed and it switches between 0 V and 5 V. If the PWM output was grounded, it remains off.
OUTPUT CURRENT SENSING
The ADP3186 provides a dedicated current sense amplifier (CSA) to monitor the total output current for proper voltage positioning versus load current and for current limit detection. Sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element such as the low-side MOSFET. This amplifier can be configured several ways depending on the objectives of the system: * * * Output inductor DCR sensing without a thermistor for lowest cost Output inductor DCR sensing with a thermistor for improved accuracy with tracking of inductor temperature Sense resistors for highest accuracy measurements
The positive input of the CSA is connected to the CSREF pin, which is connected to the output voltage. The inputs to the amplifier are summed together through resistors from the sensing element (such as the switch node side of the output inductors) to the inverting input, CSSUM.
Rev. A | Page 9 of 24
ADP3186
The feedback resistor between CSCOMP and CSSUM sets the gain of the amplifier and a filter capacitor is placed in parallel with this resistor. The gain of the amplifier is programmable by adjusting the feedback resistor to set the load line required by the microprocessor. The current information is then given as the difference of CSREF minus CSCOMP. This difference signal is used internally to offset the VID DAC for voltage positioning and as a differential input for the current limit comparator. To provide the best accuracy for sensing current, the CSA is designed to have a low offset input voltage. Also, the sensing gain is determined by external resistors so that it can be made extremely accurate. To increase the current in any given phase, make RSW for that phase larger (make RSW = 0 for the hottest phase and do not change during balancing). Increasing RSW to only 500 substantially increases the phase current. Increase each RSW value by small amounts to achieve balance, starting with the coolest phase first.
VOLTAGE CONTROL MODE
A high gain-bandwidth voltage-mode error amplifier is used for the voltage-mode control loop. The control input voltage to the positive input is set via the VID logic, according to the voltages listed in Table 4. This voltage is also offset by the droop voltage for active positioning of the output voltage as a function of current, commonly known as active voltage positioning. The output of the amplifier is the COMP pin, which sets the termination voltage for the internal PWM ramps. The negative input (FB) is tied to the output sense location with a resistor (RB) and is used for sensing and controlling the output voltage at this point. A current source from the FB pin flowing through RBB is used for setting the no-load offset voltage from the VID voltage. The no-load voltage is positive with respect to the VID DAC. The main loop compensation is incorporated into the feedback network between FB and COMP.
B
ACTIVE IMPEDANCE CONTROL MODE
For controlling the dynamic output voltage droop as a function of output current, a signal proportional to the total output current at the CSCOMP pin can be scaled to equal the droop impedance of the regulator times the output current. This droop voltage is then used to set the input control voltage to the system. The droop voltage is subtracted from the DAC reference input voltage directly to tell the error amplifier where the output voltage should be. This differs from previous implementations and allows enhanced feed-forward response.
CURRENT CONTROL MODE AND THERMAL BALANCE
The ADP3186 has individual inputs for each phase, which are used for monitoring the current in each phase. This information is combined with an internal ramp to create a current balancing feedback system, which has been optimized for initial current balance accuracy and dynamic thermal balancing during operation. This current balance information is independent of the average output current information used for positioning described previously. The magnitude of the internal ramp can be set to optimize the transient response of the system. It also monitors the supply voltage for feed-forward control for changes in the supply. A resistor connected from the power input voltage to the RAMPADJ pin determines the slope of the internal PWM ramp. Detailed information about programming the ramp is given in the Application Information section. External resistors can be placed in series with individual phases to create, if desired, an intentional current imbalance such as when one phase may have better cooling and can support higher currents. Resistors RSW1 through RSW4 (see the typical application circuit in Figure 10) can be used for adjusting thermal balance. It is best to have the ability to add these resistors during the initial design, so make sure that placeholders are provided in the layout.
SOFT START
The power-on ramp-up time of the output voltage is set with a capacitor and resistor in parallel from the DELAY pin to ground. The RC time constant also determines the current limit latch-off time, as explained in the Current Limit, Short-Circuit, and Latch-Off Protection section. In UVLO or when EN is a logic low, the DELAY pin is held at ground. After the UVLO thresh-hold is reached and EN is a logic high, the DELAY capacitor is charged with an internal 20 A current source. The output voltage follows the ramping voltage on the DELAY pin, limiting the inrush current. The soft start time depends on the value of VID DAC and CDLY, with a secondary effect from RDLY. See the Application Information section for details on setting CDLY. If EN is taken low or VCC drops below UVLO, the DELAY capacitor is reset to ground to be ready for another soft start cycle. Figure 8 shows a typical soft start sequence for the ADP3186.
Rev. A | Page 10 of 24
ADP3186
CH1 = CSREF CH2 = DELAY CH3 = COMP CH4 = PGD
The resistor has an impact on the soft start time, because the current through it adds to the internal 20 A current source. During startup when the output voltage is below 200 mV, a secondary current limit is active. This is necessary, because the voltage swing of CSCOMP cannot go below ground. This secondary current limit controls the internal COMP voltage to the PWM comparators to 2 V. This limits the voltage drop across the low-side MOSFETs through the current balance circuitry.
04914-0-008
Figure 8. Typical Start-Up Waveforms--Channel 1: PWRGD, Channel 2: CSREF, Channel 3: DELAY, Channel 4: COMP
An inherent per phase current limit protects individual phases, if one or more phases stops functioning because of a faulty component. This limit is based on the maximum normal mode COMP voltage.
CURRENT LIMIT, SHORT-CIRCUIT, AND LATCHOFF PROTECTION
The ADP3186 compares a programmable current-limit setpoint to the voltage from the output of the current sense amplifier. The level of current limit is set with the resistor from the ILIMIT pin to ground. During normal operation, the voltage on ILIMIT is 3 V. The current through the external resistor is internally scaled to give a current limit threshold of 10.4 mV/A. If the difference in voltage between CSREF and CSCOMP rises above the current limit threshold, the internal current limit amplifier controls the internal COMP voltage to maintain the average output current at the limit. After the limit is reached, the 3 V pull-up on the DELAY pin is disconnected and the external delay capacitor is discharged through the external resistor. A comparator monitors the DELAY voltage and shuts off the controller when the voltage drops below 1.8 V. The current limit latch-off delay time is, therefore, set by the RC time constant discharging from 3 V to 1.8 V. The Application Information section discusses the selection of CDLY and RDLY. Because the controller continues to cycle the phases during the latch-off delay time, if the short is removed before the 1.8 V threshold is reached, the controller returns to normal operation. The recovery characteristic depends on the state of PWRGD. If the output voltage is within the PWRGD window, the controller resumes normal operation. However, if short circuit has caused the output voltage to drop below the PWRGD threshold, a soft start cycle is initiated. The latch-off function can be reset by either removing and reapplying VCC to the ADP3186, or by pulling the EN pin low for a short time. To disable the short circuit latch-off function, the external resistor to ground should be left open, and a highvalue (>1 M) resistor should be connected from DELAY to VCC. This prevents the DELAY capacitor from discharging, so the 1.8 V threshold is never reached.
04914-0-009
Figure 9. Overcurrent Latch-Off Waveforms--Channel 1: CSREF, Channel 2: DELAY, Channel 3: COMP, Channel 4: Phase 1 Switch Node
DYNAMIC VID
The ADP3186 has the ability to dynamically change the VID input while the controller is running. This allows the output voltage to change while the supply is running and supplying current to the load. This is commonly referred to as VID on-the-fly (OTF). A VID OTF can occur under either light or heavy load conditions. The processor signals the controller by changing the VID inputs in multiple steps from the start code to the finish code. This change can be positive or negative. When a VID input changes state, the ADP3186 detects the change and ignores the DAC inputs for a minimum of 400 ns. This time prevents a false code due to logic skew while the five VID inputs are changing. Additionally, the first VID change initiates the PWRGD and CROWBAR blanking functions for a minimum of 100 s to prevent a false PWRGD or CROWBAR event. Each VID change resets the internal timer.
Rev. A | Page 11 of 24
ADP3186
Table 4. VID Codes for the ADP3186
VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Output No CPU 0.800 V 0.825 V 0.850 V 0.875 V 0.900 V 0.925 V 0.950 V 0.975 V 1.000 V 1.025 V 1.050 V 1.075 V 1.100 V 1.125 V 1.150 V 1.175 V 1.200 V 1.225 V 1.250 V 1.275 V 1.300 V 1.325 V 1.350 V 1.375 V 1.400 V 1.425 V 1.450 V 1.475 V 1.500 V 1.525 V 1.550 V
OUTPUT CROWBAR
As part of the protection for the load and output components of the supply, the PWM outputs are driven low (turning on the low-side MOSFETs) and the CROWBAR logic output goes high when the output voltage exceeds the upper crowbar threshold. This crowbar action stops once the output voltage falls below the release threshold of approximately 400 mV. Turning on the low-side MOSFETs pulls down the output as the reverse current builds up in the inductors. If the output overvoltage is due to a short in the high-side MOSFET, this action current-limits the input supply or blows its fuse, protecting the microprocessor from destruction. The CROWBAR output can be used to signal an external input crowbar or other protection circuit.
OUTPUT ENABLE AND UVLO
For the ADP3186 to begin switching, the input supply (VCC) to the controller must be higher than the UVLO threshold, and the EN pin must be higher than its logic threshold. If UVLO is less than the threshold or the EN pin is a logic low, the ADP3186 is disabled. This holds the PWM outputs at ground, shorts the DELAY capacitor to ground, and holds the ILIMIT pin at ground. In the application circuit, the ILIMIT pin should be connected to the OD pins of the ADP3110A. The ILIMIT being grounded disables the drivers such that both DRVH and DRVL are grounded. This feature is important in preventing the discharge of the output capacitors when the controller is shut off. If the driver outputs were not disabled, a negative voltage could be generated during output due to the high current discharge of the output capacitors through the inductors.
POWER GOOD MONITORING
The power good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open-drain output whose high level (when connected to a pull-up resistor) indicates that the output voltage is within the nominal limits specified in the specifications in Table 4 based on the VID voltage setting. PWRGD goes low if the output voltage is outside this specified range, if all the VID DAC inputs are high, or whenever the EN pin is pulled low. PWRGD is blanked during a VID OTF event for a period of 100 s to prevent false signals during the time the output is changing.
Rev. A | Page 12 of 24
ADP3186
L1 1.6H VIN 12V VIN RTN C1 C2 C3 2200F/16V 3 NICHICON PW SERIES
+
+
+
D1 1N4148WS
C6 4.7F C5 U2 ADP3110A 100nF
1 BST 2 IN 3 OD 4 VCC
DRVH 8 SW 7 PGND 6 DRVL 5
Q1 NTD60N02
820F/4V 8 L2 OS-CON SP SERIES 600nH/1.6m 12m ESR (EACH) C7 4.7nF R1 2.2 + +
VCC(CORE) 0.8V - 1.55V
C4 1F
Q2 NTD110N02
VCC(CORE) RTN C23 C30
D2 1N4148WS
C9 U3 100nF ADP3110A
1 BST 2 IN 3 OD 4 VCC
C10 4.7F
Q4 NTD60N02
10F 8 MLCC IN SOCKET
DRVH 8 SW 7 PGND 6 DRVL 5
L3 600nH/1.6m C11 4.7nF R2 2.2
Q5 NTD110N02
C8 1F
D3 1N4148WS
C13 U4 100nF ADP3110A
1 BST 2 IN 3 OD 4 VCC
C14 4.7F
Q7 NTD60N02
DRVH 8 SW 7 PGND 6 DRVL 5
L4 600nH/1.6m C15 4.7nF R3 2.2 RTH1 100k, 1%
C12 1F
Q8 NTD110N02
D4 1N4148WS
R4 10
C16 1F
R5 332k
U1
ADP3186
VCC 28 PWM1 27 PWM2 26 PWM3 25 PWM4 24 SW1 23 SW2 22 SW3 21 SW4 20 GND 19 CSCOMP 18 CSSUM 17 CSREF 16 ILIMIT 15 C21 C22 1.5nF 2.2nF R11 R10 35.7k 73.2k R12 147k R13 147k R14 147k
1 VID4 2 VID3
FROM CPU
3 VID2 4 VID1 5 VID0
CROWBAR C17 680nF C19 27pF POWER GOOD ENABLE R6 2.00k C18 680pF R7 8.45k
6 CROWBAR 7 FBRTN 8 FB 9 COMP 10 PWRGD 11 EN 12 DELAY
C20 39nF
R8 390k R9 187k
13 RT 14 RAMPADJ
Figure 10. Typical VR 10.1 Application Circuit
Rev. A | Page 13 of 24
04914-0-010
R15 280k
ADP3186 APPLICATION INFORMATION
The design parameters for a typical AMD Opteron CPU application are as follows: * * * * * * * * * Input voltage (VIN) = 12 V VID setting voltage (VVID) = 1.500 V Duty cycle (D) = 0.125 Maximum static output voltage error (VSRER) = 50 mV Maximum dynamic output voltage error (VDRER) = 70 mV Error voltage allowed for controller and ripple (VRERR) = 20 mV Maximum output current (IO) = 56 A Maximum output current step (IO) = 24 A Static output drop resistance (RO) based on 1. No load output voltage set at upper output voltage limit. VONL = VVID + VSERR - VRERR = 1.530 V Full load output voltage set at lower output voltage limit. VOFL = VVID - VSERR + VRERR = 1.470 V RO = (VONL - VOFL)/IO = (1.53 V - 1.47 V)/56 A = 1.1 m where 4.7 pF and 27 k are internal IC component values. For good initial accuracy and frequency stability, a 1% resistor is recommended. Alternatively, the value for RT can be calculated using
RT = 1 - 27 k n x f SW x 4.7 pF
(1)
SOFT START AND CURRENT LIMIT LATCH-OFF DELAY TIMES
Because the soft start and current limit latch-off delay functions share the DELAY pin, these two parameters must be considered together. The first step is to set CDLY for the soft start ramp. This ramp is generated with a 20 A internal current source. The value of RDLY has a second-order impact on the soft start time, because it sinks part of the current source to ground. However, as long as RDLY is kept greater than 200 k, this effect is minor. The value for CDLY can be approximated using
2.
VVID C DLY = 20 A - 2 x R DLY
t SS x V VID
(2)
3. *
Dynamic output drop resistance (ROD) based on 1. Output current step to no load with output voltage set at upper output dynamic voltage limit. VONLD = VVID + VDERR - VRERR = 1.550 V Output voltage prior to load change (at IOUT = IO). VOL = VONL - (IO x RO) = 1.504 V ROD = (VONLD - VOL)/IO = (1.55 V - 1.504 V)/24 A = 1.9 m
where tSS is the desired soft start time. Assuming an RDLY of 390 k and a desired soft start time of 3 ms, CDLY is 36 nF. The closest standard value for CDLY is 39 nF. Once CDLY is chosen, RDLY can be calculated for the current limit latch-off time using
R DLY = 1.96 x t DELAY C DLY
(3)
2. 3. * *
Number of phases (n) = 3 Switching frequency per phase (fSW) = 330 kHz
If the result for RDLY is less than 200 k, a smaller soft start time should be considered by recalculating the equation for CDLY, or a longer latch-off time should be used. RDLY should never be less than 200 k. In this example, a delay time of 8 ms results in RDLY equal to 402 k. The closest standard 5% value is 390 k.
INDUCTOR SELECTION
The choice of inductance for the inductor determines the ripple current in the inductor. Less inductance leads to more ripple current, which increases the output ripple voltage and conduction losses in the MOSFETs, but allows using smaller inductors and, for a specified peak-to-peak transient deviation, less total output capacitance. Conversely, a higher inductance means lower ripple current and reduced conduction losses, but requires larger inductors and more output capacitance for the same peak-to-peak transient deviation. In any multiphase converter, a practical value for the peak-to-peak inductor ripple current is less than 50% of the maximum dc current in the same inductor. Equation 4 shows the relationships among the inductance, oscillator frequency, and peak-to-peak ripple current in the inductor.
SETTING THE CLOCK FREQUENCY
The ADP3186 uses a fixed-frequency control architecture. The frequency is set by an external timing resistor (RT). The clock frequency and the number of phases determine the switching frequency per phase, which relates directly to switching losses, and the sizes of the inductors, and the sizes of the input and output capacitors. With n = 3 for three phases, a clock frequency of 990 kHz sets the switching frequency (fSW) of each phase to 330 kHz, which represents a practical trade-off between the switching losses and the sizes of the output filter components. Figure 6 shows that, to achieve an 990 kHz oscillator frequency, the correct value for RT is 187 k.
Rev. A | Page 14 of 24
ADP3186
Equation 5 can be used to determine the minimum inductance based on a given output ripple voltage.
IR = VVID x (1 - D ) f SW x L
f SW x V RIPPLE
Many useful magnetics design references are available for quickly designing a power inductor, such as * Magnetic Designer Software Intusoft (www.intusoft.com) Designing Magnetic Components for High-Frequency DCDC Converters, by William T. McLyman, Kg Magnetics, Inc., ISBN 1883107008
(4) * (5)
L
VVID x R OD x (1 - (n x D ))
Solving Equation 5 for a 10 mV p-p output ripple voltage yields
L 1.5 V x 1.9 m x (1 - 0.375 ) 330 kHz x 10 mV
Selecting a Standard Inductor
The following power inductor manufacturers can provide design consultation and deliver power inductors optimized for high power applications upon request: * Coilcraft (847) 639-6400 www.coilcraft.com Coiltronics (561) 752-5000 www.coiltronics.com Sumida Corporation (510) 668-0660 www.sumida.com Vishay (402) 563-6866 www.vishay.com
= 540 nH
If the resulting ripple voltage is less than that designed for, the inductor can be made smaller until the ripple value is met. This allows optimal transient response and minimum output decoupling. The smallest possible inductor should be used to minimize the number of output capacitors. For this example, choosing a 600 nH inductor is a good starting point and gives a calculated ripple current of 6.6 A. The inductor should not saturate at the peak current of 22 A and should be able to handle the sum of the power dissipation caused by the average current of 18.7 A in the winding and core loss. Another important factor in the inductor design is the DCR, which is used for measuring the phase currents. A large DCR can cause excessive power losses, while too small a value can lead to increased measurement error. A good rule is to have the DCR be about 1 to 11/2 times the droop resistance (RO). The example uses an inductor with a DCR of 1.6 m.
*
*
*
OUTPUT DROOP RESISTANCE
The design requires that the regulator output voltage measured at the CPU pins drop when the output current increases. The specified voltage drop corresponds to the static output droop resistance (RO). The output current is measured by summing the voltage across each inductor and passing the signal through a low-pass filter. This summer filter is the CS amplifier configured with resistors RPH(X) (summers), and RCS and CCS (filter). The output resistance of the regulator is set by the following equations, where RL is the DCR of the output inductors:
DESIGNING AN INDUCTOR
Once the inductance and DCR are known, the next step is to either design an inductor or to find a standard inductor that comes as close as possible to meeting the overall design goals. It is also important to have the inductance and DCR tolerance specified to control the accuracy of the system. 20% inductance and 8% DCR (at room temperature) are reasonable tolerances that most manufacturers can meet. The first decision in designing the inductor is to choose the core material. Several possibilities for providing low core loss at high frequencies include the powder cores (for example, Kool-M(R) from Magnetics, Inc. or from Micrometals) and the gapped soft ferrite cores (for example, 3F3 or 3F4 from Philips). Low frequency powdered iron cores should be avoided due to their high core loss, especially when the inductor value is relatively low and the ripple current is high. The best choice for a core geometry is a closed-loop type such as a potentiometer core, PQ, U, E core, or toroid. A good compromise between price and performance is a core with a toroidal shape.
RO =
RCS RPH ( x )
x RL
(6)
C CS =
L R L x RCS
(7)
One has the flexibility of choosing either RCS or RPH(X). It is best to select RCS equal to 100 k, and then solve for RPH(X) by rearranging Equation 6:
Rev. A | Page 15 of 24
ADP3186
RPH ( x ) = RL x RCS RO 1.6 m 1.1 m x 100 k = 145.5 k
2.
RPH ( x ) =
Based on the type of NTC, find its relative resistance value at two temperatures. The temperatures that work well are 50C and 90C. These resistance values are called A (RTH(50C)/RTH(25C)) and B (RTH(90C)/RTH(25C)). Note that the NTC's relative value is always 1 at 25C. Find the relative value of RCS required for each of these temperatures. This is based on the percentage change needed, which in this example is initially 0.39%/C. These are called r1 (1/(1 + TC x (T1 - 25))) and r2 (1/(1 + TC x (T2 - 25))), where TC = 0.0039 for copper. T1 = 50C and T2 = 90C are chosen. From this, one can calculate that r1 = 0.9112 and r2 = 0.7978. Compute the relative values for RCS1, RCS2, and RTH using
3. Next, use Equation 6 to solve for CCS. 600 nH 1.6 m x 100 k
CCS =
= 3.75 nF
It is best to have a dual location for CCS in the layout, so that standard values can be used in parallel to get as close as possible to the value desired. For best accuracy, CCS should be a 5% or 10% NPO capacitor. This example uses a 5% combination for CCS of 1.5 nF and 2.2 nF in parallel. Recalculating RPH(X) using this capacitor combination yields a 1% value of 147 k.
4.
rCS2 =
( A - B ) x r1 x r2 - A x (1 - B ) x r2 + B x (1 - A ) x r1 A x (1 - B ) x r1 - B x (1 - A ) x r2 - ( A - B )
(1 - A ) A 1 - 1 - rCS2 r1 - rCS2
1 1 1 - 1 - rCS2 rCS1 (8)
INDUCTOR DCR TEMPERATURE CORRECTION
When the inductor's DCR is used as the sense element and copper wire is the source of the DCR, one needs to compensate for temperature changes of the inductor's winding. Fortunately, copper has a well-known temperature coefficient (TC) of 0.39%/C. If RCS is designed to have an opposite and equal percentage change in resistance to that of the wire, it cancels the temperature variation of the inductor's DCR. Due to the nonlinear nature of NTC thermistors, resistors RCS1 and RCS2 are needed. See Figure 11 to linearize the NTC and produce the desired temperature tracking.
PLACE AS CLOSE AS POSSIBLE TO NEAREST INDUCTOR OR LOW-SIDE MOSFET
R TH TO SWITCH NODES TO V OUT SENSE
rCS1 =
rTH =
5.
Calculate RTH = rTH x RCS, then select the closest value of thermistor available. Also compute a scaling factor k based on the ratio of the actual thermistor value used relative to the computed one: RTH ( ACTUAL ) k= (9) RTH (CALCULATED ) Calculate values for RCS1 and RCS2 using Equation 10: RCS1 = RCS x k x rCS1
6.
R PH1 R PH2 R PH3
ADP3186
CSCOMP
18 C CS1 C CS2 R CS1 R CS2
RCS2 = RCS x ((1 - k ) + (k x rCS2 ))
KEEP THIS PATH AS SHORT AS POSSIBLE AND WELL AWAY FROM SWITCH NODE LINES
04914-0-011
(10)
CSSUM
17
CSREF
16
Figure 11. Temperature Compensation Circuit Values
The following procedure and expressions yield values to use for RCS1, RCS2, and RTH (the thermistor value at 25C) for a given RCS value: 1. Select an NTC based on type and value. Because the value has not yet been found, start with a thermistor with a value close to RCS. The NTC should also have an initial tolerance of better than 5%.
For this example, RCS has been calculated to be 100 k, so start with a thermistor value of 100 k. Looking through available 0603 size thermistors, one finds a Vishay NTHS0603N01N1003JR NTC thermistor with A = 0.3602 and B = 0.09174. From these, one can compute rCS1 = 0.3796, rCS2 = 0.7195, and rTH = 1.0751. Solving for RTH yields 107.51 k, so 100 k is chosen, making k = 0.9302. Finally, one finds that RCS1 and RCS2 are 35.3 k and 73.9 k. Choosing the closest 1% resistor values yields a choice of 35.7 k and 73.2 k.
OUTPUT OFFSET
The AMD specification requires that at no load the nominal output voltage of the regulator be offset to a value higher than the nominal voltage corresponding to the VID code.
Rev. A | Page 16 of 24
ADP3186
The offset is set by a constant current source flowing into of the FB pin (IFB) and flowing through RB. The value of RB can be found using Equation 11:
B
RB =
VONL - VVID I FB
This example uses a combination of MLC capacitors (CZ = 80 F). The VID on-the-fly step change is from 1.5 V to 0.8 V (making VV = 700 mV) in 100 s with a setting error of 3%. Solving for the bulk capacitance yields
RB =
1.53 V - 1.5 V 15 A
600 nH x 24 A C x ( MIN ) - 80 F = 1.6 mF 3 x 1.9 m x 1.5 V
= 2.00 k
(11)
C x ( MAX )
600 nH x 700 mV 3 x 3.52 x 1.1m x 1.5 V
x
The closest standard 1% resistor value is 2 k.
COUT SELECTION
The required output decoupling for the regulator is typically recommended by AMD for various processors and platforms. One can also use some simple design guidelines to determine what is required. These guidelines are based on having both bulk and ceramic capacitors in the system. First select the total amount of ceramic capacitance. This is based on the number and type of capacitor to be used. The best location for ceramics is inside the socket. Others can be placed along the outer edge of the socket as well. Combined ceramic values of 30 F to 100 F are recommended, usually made up of multiple 10 F or 22 F capacitors. Select the number of ceramics and find the total ceramic capacitance (CZ). Next, there is an upper limit imposed on the total amount of bulk capacitance (CX) when one considers the VID on-the-fly voltage stepping of the output (voltage step VV in time tV with error of VERR). A lower limit is based on meeting the capacitance for load release for a given maximum load step IO and a maximum allowable overshoot. The total amount of load release voltage is given as VO = IO x ROD.
2 100 s x 1.5 V x 3 x 3.5 x 1.1 m - 1 - 80 F = 20.4 mF 1+ 700 mV x 600 nH
where k = 3.5. Using eight 820 F OS-CON capacitors with a typical ESR of 12 m each yields CX = 6.56 mF with an RX = 1.5 m. One last check should be made to ensure that the ESL of the bulk capacitors (LX) is low enough to limit the high frequency ringing during a load change. This is tested using
L x Q 2 x C z x R OD 2 L x 2 x 80 F x (1.9 m )2 = 580 pH
(14)
where Q is limited to the square root of 2 to ensure a critically damped system. In this example, LX is approximately 500 pH for the eight OS-CON capacitors, which satisfies this limitation. If the LX of the chosen bulk capacitor bank is too large, the number of ceramic capacitors might need to be increased, if there is excessive ringing. One should note that for this multimode control technique, all ceramic designs can be used as long as the conditions of Equations 11, 12, and 13 are satisfied.
L x IO - Cz C x ( MIN ) nx R xV VID OD
C x ( MAX )
(12)
POWER MOSFETS
For this example, the N channel power MOSFETs have been selected for one high-side switch and two low-side switches per phase. The main selection parameters for the power MOSFETs are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive voltage (the supply voltage to the ADP3110A) dictates whether standard threshold or logic-level threshold MOSFETs must be used. With VGATE ~10 V, logic-level threshold MOSFETs (VGS(TH) < 2.5 V) are recommended. The maximum output current (IO) determines the RDS(ON) requirement for the low-side (synchronous) MOSFETs. With the ADP3186, currents are balanced between phases, therefore the current in each low-side MOSFET is the output current divided by the total number of MOSFETs (nSF).
2 nKRO V V L - 1 - C Z (13) x V x 1 + t v x VID x 2 VV L nK 2 RO VVID
V where K = l n ERR V V

To meet the conditions of these expressions and transient response, the ESR of the bulk capacitor bank (RX) should be less than or equal to the dynamic droop resistance (ROD). If the CX(MIN) is larger than CX(MAX), the system cannot meet the VID on-the-fly specification and might require the use of a smaller inductor or more phases (and might have to increase the switching frequency to keep the output ripple the same).
Rev. A | Page 17 of 24
ADP3186
With conduction losses being dominant, the following expression shows the total power being dissipated in each synchronous MOSFET in terms of the ripple current per phase (IR) and average total output current (IO): It is interesting to note that adding more main MOSFETs (nMF) does not help the switching loss per MOSFET, because the additional gate capacitance slows switching. The best way to reduce switching loss is to use lower gate capacitance devices. The conduction loss of the main MOSFET is given by the following equation, where RDS(MF) is the on resistance of the MOSFET:
PSF
I = (1 - D ) x O n SF
1 n IR + x 12 n SF
2

2
x R DS(SF ) (15)
Knowing the maximum output current being designed for and the maximum allowed power dissipation, one can find the required RDS(ON) for the MOSFET. For D-PAK MOSFETs up to an ambient temperature of 50C, a safe limit for PSF is 1 W to 1.5 W at 120C junction temperature. Thus, for this example (56 A maximum), RDS(SF) < 4.8 m. This RDS(SF) is also at a junction temperature of about 120C, so one needs to make sure to account for this when making this selection. This example uses one low-side MOSFET at 4.8 m at 120C. Another important factor for the synchronous MOSFET is the input capacitance and feedback capacitance. The ratio of the feedback to input needs to be small (less than 10% is recommended) to prevent accidental turn-on of the synchronous MOSFETs when the switch node goes high. Also, the time to switch the synchronous MOSFETs off should not exceed the nonoverlap dead time of the MOSFET driver (40 ns typical for the ADP3110A). The output impedance of the driver is approximately 2 , and the typical MOSFET input gate resistances are about 1 to 2 , so a total gate capacitance of less than 6000 pF should be adhered to. Because there is one MOSFET, the input capacitance for the synchronous MOSFET should be limited to 6000 pF. The high-side (main) MOSFET must be able to handle two main power dissipation components: conduction and switching losses. The switching loss is related to the amount of time it takes for the main MOSFET to turn on and off, and to the current and voltage that are being switched. Basing the switching speed on the rise and fall time of the gate driver impedance and MOSFET input capacitance, the following expression provides an approximate value for the switching loss per main MOSFET, where nMF is the total number of main MOSFETs:
PS ( MF ) = 2 x f SW x VCC x I O n MF
I PC ( MF ) = D x O n MF
1 nx IR + x 12 n MF
2

2
x R DS( MF ) (17)
Typically, for main MOSFETs, the highest speed (low CISS) device is preferred, but these usually have higher on resistance. Select a device that meets the total power dissipation (about 1.5 W for a single D-PAK) when combining the switching and conduction losses. For this example, an NTD60N02 was selected as the main MOSFET (three total; nMF = 3), with a CISS = 948 pF (max), and RDS(MF) = 11.2 m (max at TJ = 120C), and an NTD110N02 was selected as the synchronous MOSFET (three total; nSF = 3), with CISS = 2710 pF (max), and RDS(SF) = 4.8 m (max at TJ = 120C). The synchronous MOSFET CISS is less than 6000 pF, satisfying that requirement. Solving for the power dissipation per MOSFET at IO = 56 A and IR = 6.6 A yields 913 mW for each synchronous MOSFET and 1.48 W for each main MOSFET. One last issue to consider is the power dissipation in the driver for each phase. This is best described in terms of the QG for the MOSFETs and is given by the following equation, where QGMF is the total gate charge for each main MOSFET and QGSF is the total gate charge for each synchronous MOSFET: f PDRV = SW x (n MF x Q GMF + n SF x Q GSF ) + I CC x VCC 2 x n (18) Also shown is the standby dissipation factor (ICC x VCC) for the driver. For the ADP3110A, the maximum dissipation should be less than 400 mW. In this example, with ICC = 7 mA, QGMF = 16 nC, and QGSF = 48 nC, one finds 211 mW in each driver, which is below the 400 mW dissipation limit. See the ADP3110A data sheet for more details.
x RG x
n MF x C ISS n
(16)
RAMP RESISTOR SELECTION
The ramp resistor (RR) is used for setting the size of the internal PWM ramp. The value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. The following expression is used for determining the optimum value:
where: RG is the total gate resistance (2 for the ADP3110A and about 1 for typical high speed switching MOSFETs, making RG = 3 ). CISS is the input capacitance of the main MOSFET.
Rev. A | Page 18 of 24
ADP3186
RR = AR x L 3 x A D x R DS x C R (19) RR = where: AR is the internal ramp amplifier gain. AD is the current balancing amplifier gain. RDS is the total low-side MOSFET on resistance. CR is the internal ramp capacitor value. The closest standard 1% resistor value is 332 k. The internal ramp voltage magnitude can be calculated by using VR = A R x (1 - D ) x VVID R R x C R x f SW (20) VR = 0.2 x (1 - 0.125) x 1.5 V 332 k x 5 pF x 330 kHz = 480 m V
I PHLIM
In this example, choosing a peak current limit of 100 A for ILIM results in RLIM = 284 k, for which 280 k is chosen as the nearest 1% value. The per-phase current limit described in the Current Limit, Short-Circuit, and Latch-Off Protection section is determined by
VCOMP ( MAX ) - VRT - VBIAS AD x RDS( MAX )
0.2 x 600 nH 3 x 5 x 4.8 m x 5 pF
= 333 k
-
IR 2
(23)
For the ADP3186, the maximum COMP voltage (VCOMP(MAX)) is 3.3 V, the COMP pin bias voltage (VBIAS) is 1.2 V, and the current balancing amplifier gain (AD) is 5. Using VR of 560 mV and RDS(MAX) of 4.8 m (low-side on resistance at 150C), one finds a per-phase peak current limit of 61 A. Although this number may seem high, this current level can be reached only with an absolute short at the output, and the current limit latchoff function shuts down the regulator before overheating can occur. This limit can be adjusted by changing the ramp voltage (VR), but make sure not to set the per-phase limit lower than the average per-phase current (ILIM/n). The per-phase initial duty cycle limit is determined by
D MAX = D x VCOMP ( MAX ) - VBIAS VRT
The size of the internal ramp can be made larger or smaller. If it is made larger, stability and transient response improve, but thermal balance degrades. Likewise, if the ramp is made smaller, thermal balance improves at the sacrifice of transient response and stability. The factor of three in the denominator of Equation 19 sets a ramp size that gives an optimal balance for good stability, transient response, and thermal balance.
(24)
In this example, the maximum duty cycle is 0.47.
COMP PIN RAMP
A ramp signal on the COMP pin is due to the droop voltage and output voltage ramps. This ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the PWM input:
V RT =
FEEDBACK LOOP COMPENSATION DESIGN
Optimized compensation of the ADP3186 allows the best possible response of the regulator's output to a load change. The basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible frequency range, including dc, and equal to the droop resistances (RO and ROD). With the resistive output impedance, the output voltage droops in proportion to the load current at any load current slew rate. This ensures optimal positioning and helps to minimize the output decoupling. With the multimode feedback structure of the ADP3186, the feedback compensation must be set so that the converter's output impedance works in parallel with the output decoupling to meet this goal. Several poles and zeros created by the output inductor and decoupling capacitors (output filter) need to be compensated for. A type-three compensator on the voltage feedback is adequate for proper compensation of the output filter. Equations 25 to 29 are intended to yield an optimal starting point for the design; some adjustments might be necessary to account for PCB and component parasitic effects.
(RO + ROD ) x (1 - n x D ) 1 - nx f SW x C X x R O x R OD
VR

(21)
In this example, the overall ramp signal is 560 mV.
CURRENT LIMIT SETPOINT
To select the current limit setpoint, first find the resistor value for RLIM. The current limit threshold for the ADP3186 is set with a 3 V source (VLIM) across RLIM with a gain of 10.4 mV/A (ALIM). RLIM can be found using
RLIM = ALIM x VLIM I LIM x RO
(22)
For values of RLIM greater than 500 k, the current limit might be lower than expected, so some adjustment of RLIM might be needed. Here, ILIM is the average current limit for the output of the supply.
Rev. A | Page 19 of 24
ADP3186
The first step is to compute the time constants for all the poles and zeros in the system:
R e = n x ROD + A D x R DS + R L x V RT VVID
+
(RO + ROD ) x L x (1 - n x D) x V RT
n x C X x RO x ROD x VVID
+
R e = 3 x 1 .9 m + 5 x 4.8 m +
1.6 m x 0.56 V 1.5 V
(1.1 m+ 1.9 m) x 600 nH x (1 - 0.375)x 0.56 V
3 x 6.56 mF x 1 .1 m x 1.9 m x 1.5 V
= 40.5 m
(25)
Ta = C X x (ROD - R ' ) +
500 pH 1.9 m - 0.6 m R - R' LX x OD = 6.56 mF x (1.9 m - 0.6 m ) + x = 8.76 s 1 .9 m 1.5 m ROD RX
(26) (27)
Tb = (R X + R'- ROD ) x C X = (1.5 m + 0.6 m - 1.9 m ) x 6.56 mF = 1.31 s
A D x R DS V RT x L - 2 x f SW Tc = VVID x R e
Td =
2 C X x C Z x ROD

5 x 4.8 m 0.56 V x 600 nH- 2 x 330 kHz = = 5.2 s 1.5 V x 40.5 m
=
6.56 mF x (1.9 m - 0.6 m ) + 80 F x 1.9 m 6.56 mF x 80 F x (1.9 m ) 2
(28)
C X x (ROD - R ' ) + C Z x ROD
= 218 ns
(29)
where, for the ADP3186, R' is the PCB resistance from the bulk capacitors to the ceramics and where RDS is the total low-side MOSFET on resistance per phase. In this example, AD is 5, VRT equals 0.56 V, R' is approximately 0.6 m (assuming a 4-layer, 1 oz motherboard), and LX is 500 pH for the eight OS-CON capacitors. The compensation values can then be solved using
CIN SELECTION AND INPUT CURRENT di/dt REDUCTION
In continuous inductor current mode, the source current of the high-side MOSFET is approximately a square wave with a duty ratio equal to n x VOUT/VIN and an amplitude of 1 nth the maximum output current. To prevent large voltage transients, a low ESR input capacitor, sized for the maximum rms current, must be used. The maximum rms capacitor current is given by
I Crms = D x I O x 1 -1 NxD
CA =
n x ROD x Ta Re x R B
(30)
CA =
RA = CB =
3 x 1.9 m x 8.76 s 40.5 m x 2 k
= 616 pF
I Crms
1 = 0.125 x 56 A x - 1 = 9.05 A 3 x 0.125
(34)
5.2 s Tc = = 8.44 k C A 616 pF Tb RB Td RA = 1.31 s 2 k 655 pF
(31)
(32)
C FB =
=
218 ns = 25.8 pF 8.44 k
(33)
Note that the capacitor manufacturer's ripple current ratings are often based on only 2,000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors can be placed in parallel to meet size or height requirements in the design. In this example, the input capacitor bank is formed by three 2,200 F, 16 V aluminum electrolytic capacitors with a ripple rating of 3.5 A each. To reduce the input current di/dt to a level below the recommended maximum of 0.1 A/s, an additional small inductor (L > 1 H @ 15 A) should be inserted between the converter and the supply bus. That inductor also acts as a filter between the converter and the primary power source.
These are the starting values prior to tuning the design to account for layout and other parasitic effects (see the Tuning Procedure section). The final values selected after tuning are CA = 680 pF RA = 8.45 k DB = 860 pF CFB = 27 pF
B
Rev. A | Page 20 of 24
ADP3186
TUNING PROCEDURE
To tune the AD3186, follow these steps: 1. 2. Build a circuit based on the compensation values computed from the design spreadsheet. Hook up the dc load to circuit, turn it on, and verify its operation. Also check for jitter at no-load and full-load.
AC Loadline Setting
11. Remove the dc load from the circuit and hook up the dynamic load. 12. Hook up the scope to the output voltage and set it to dc coupling with the time scale at 100 s/div. 13. Set the dynamic load for a transient step of about 24 A at 1 kHz with 50% duty cycle. 14. Measure the output waveform (you might have to use dc offset on scope to see the waveform). Try to use a vertical scale of 100 mV/div or finer. This waveform should look similar to Figure 12. 15. Use the horizontal cursors to measure VACDRP and VDCDRP as shown. Do not measure the undershoot or overshoot that happens immediately after the step. 16. If VACDRP and VDCDRP are different by more than a few mV, use Equation 38 to adjust CCS. You might need to parallel different values to get the right one, because the standard capacitor values available are limited. It is a good idea to have locations for two capacitors in the layout for this.
CCS ( NEW ) = CCS (OLD ) x VACDRP VDCDRP
DC Loadline Setting
3. 4. Measure the output voltage at no-load (VNL). Verify that it is within tolerance. Measure the output voltage at full-load cold (VFLCOLD). Let the board sit for ~10 minutes at full-load, and then measure the output (VFLHOT). If there is a change of more than a few mV, adjust RCS1 and RCS2 using Equations 35 and 37.
RCS2 ( NEW ) = RCS2 (OLD ) x VNL - VFLCOLD VNL - VFLHOT
(35)
5. 6.
Repeat Step 4 until the cold and hot voltage measurements remain the same. Measure the output voltage from no-load to full-load using 5 A steps. Compute the loadline slope for each change, and then average them to determine the overall loadline slope (ROMEAS). If ROMEAS is off from RO by more than 0.05 m, use the following to adjust the RPH values:
RPH ( NEW ) = RPH (OLD ) x ROMEAS RO
(38)
7.
17. Repeat Steps 11 to 13 and repeat the adjustments, if necessary. Once complete, do not change CCS for the remainder of the procedure. (36) 18. Set the dynamic load step to the maximum step size (do not use a step size larger than needed) and verify that the output waveform is square, which means that VACDRP and VDCDRP are equal.
8. 9.
Repeat Steps 6 and 7 to check the loadline, and repeat adjustments, if necessary. Once dc loadline adjustment is complete, do not change RPH, RCS1, RCS2, or RTH for the remainder of the procedure.
10. Measure the output ripple at no-load and full-load with a scope, and make sure that it is within specifications.
VACDRP VDCDRP
Figure 12. AC Loadline Waveform
RCS1( NEW ) =
RCS1(OLD ) x RTH (25 C ) + RCS1(OLD ) - RCS2 ( NEW ) x RCS1(OLD ) - RTH (25 C )
(
1 RCS1(OLD ) + RTH (25 C )
04914-0-012
)(
)
-
1 RTH (25 C )
(37)
Rev. A | Page 21 of 24
ADP3186
Initial Transient Setting
19. With the dynamic load still set at the maximum step size, expand the scope time scale to see 2 s/div to 5 s/div. The waveform may have two overshoots and one minor undershoot (see Figure 13). Here, VDROOP is the final desired value. Because the ADP3186 turns off all the phases (switches inductors to ground), there is no ripple voltage present during load release. Therefore, you do not have to add headroom for ripple, allowing your load release VTRANREL to be larger than VTRAN1 by the amount of ripple, and still meet specifications. If VTRAN1 and VTRANREL are less than the desired final droop, this implies that capacitors can be removed. When removing capacitors, check the output ripple voltage as well to make sure that it is still within specifications.
VDROOP
LAYOUT AND COMPONENT PLACEMENT
The following guidelines are recommended for optimal performance of a switching regulator in a PC system.
General Recommendations
VTRAN1
04914-0-013
VTRAN2
Figure 13. Transient Setting Waveform
20. If both overshoots are larger than desired, try making the following adjustments. Note that, if these adjustments do not change the response, you are limited by the output decoupling. Check the output response each time you make a change as well as the switching nodes to make sure that the response is still stable. 21. Make the ramp resistor larger by 25% (RRAMP). 22. For VTRAN1, increase CB or increase the switching frequency.
B
For good results, a PCB with at least four layers is recommended. This provides the needed versatility for control circuitry interconnections with optimal placement, power planes for ground, input, and output power, and wide interconnection traces in the remainder of the power delivery current paths. Keep in mind that each square unit of 1 oz copper trace has a resistance of ~0.53 m at room temperature. Whenever high currents must be routed between PCB layers, vias should be used liberally to create several parallel current paths, so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. If critical signal lines (including the output voltage sense lines of the ADP3186) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. An analog ground plane should be used around and under the ADP3186 as a reference for the components associated with the controller. This plane should be tied to the nearest output decoupling capacitor ground and should not be tied to any other power circuitry to prevent power currents from flowing in it. The components around the ADP3186 should be located close to the controller with short traces. The most important traces to keep short and away from other traces are the FB and CSSUM pins. The output capacitors should be connected as close as possible to the load (or connector), for example, a microprocessor core, that receives the power. If the load is distributed, the capacitors should also be distributed and generally be in proportion to where the load tends to be more dynamic.
23. For VTRAN2, increase RA and decrease CA by 25%. 24. For load release (see Figure 14), if VTRANREL is larger than VTRAN1 (see Figure 13), there is not enough output capacitance. You need more capacitance or you have to make the inductor values smaller. (If you change inductors, you need to start the design again using the spreadsheet and this tuning procedure.)
VTRANREL
VDROOP
04914-0-014
Figure 14. Transient Setting Waveform
Avoid crossing any signal lines over the switching power path loop, described in the Power Circuitry Recommendations section.
Rev. A | Page 22 of 24
ADP3186
Power Circuitry Recommendations
The switching power path should be routed on the PCB to encompass the shortest possible length to minimize radiated switching noise energy (EMI) and conduction losses in the board. Failure to take proper precautions often results in EMI problems for the entire PC system as well as noise-related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs including all interconnecting PCB traces and planes. Using short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it accommodates the high current demand with minimal voltage loss. Whenever a power dissipating component, for example, a power MOSFET, is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for this are improved current rating through the vias and improved thermal performance from vias extended to the opposite side of the PCB, where a plane can more readily transfer the heat to the air. Make a mirror image of any pad being used to heat sink the MOSFETs on the opposite side of the PCB to achieve the best thermal dissipation to the air around the board. To further improve thermal performance, use the largest possible pad area. The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load. For best EMI containment, a solid power ground plane should be used as one of the inner layers extending fully under all the power components.
Signal Circuitry Recommendations
The output voltage is sensed and regulated between the FB pin and the FBRTN pin, which connect to the signal ground at the load. To avoid differential mode noise pickup in the sensed signal, the loop area should be small. Therefore, the FB and FBRTN traces should be routed adjacent to each other on top of the power ground plane back to the controller. The feedback traces from the switch nodes should be connected as close as possible to the inductor. The CSREF signal should be connected to the output voltage at the nearest inductor to the controller.
Rev. A | Page 23 of 24
ADP3186 OUTLINE DIMENSIONS
9.80 9.70 9.60
28
15
4.50 4.40 4.30 6.40 BSC
1 14
PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX 8 0 0.75 0.60 0.45
SEATING PLANE
0.20 0.09
COMPLIANT TO JEDEC STANDARDS MO-153AE
Figure 15. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters
0.390 BSC
28
15
0.154 BSC
1 14
0.236 BSC
PIN 1 0.065 0.049 0.069 0.053 8 0
0.010 0.004 COPLANARITY 0.004
0.025 BSC
0.012 0.008
SEATING PLANE
0.010 0.006
0.050 0.016
COMPLIANT TO JEDEC STANDARDS MO-137-AF
Figure 16. 28-Lead Shrink Small Outline Package [QSOP] (RQ-28) Dimensions shown in millimeters
ORDERING GUIDE
Model ADP3186JRUZ-REEL 1 ADP3186JRQZ-REEL1
1
Temperature Range 0C to 85C 0C to 85C
Package Description 28-Lead TSSOP 28-Lead QSOP
Package Option RU-28 RQ-28
Quantity per Reel 2500 2500
Z = Pb-free part.
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04914-0-3/06(A)
Rev. A | Page 24 of 24

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